SABRE: A bio-inspired fault-tolerant electronic architecture

As electronic devices become increasingly complex, ensuring their reliable, fault-free operation is becoming correspondingly more challenging. It can be observed that, in spite of their complexity, biological systems are highly reliable and fault tolerant. Hence, we are motivated to take inspiration for biological systems in the design of electronic ones. In SABRE (self-healing cellular architectures for biologically inspired highly reliable electronic systems), we have designed a bio-inspired fault-tolerant hierarchical architecture for this purpose. As in biology, the foundation for the whole system is cellular in nature, with each cell able to detect faults in its operation and trigger intra-cellular or extra-cellular repair as required. At the next level in the hierarchy, arrays of cells are configured and controlled as function units in a transport triggered architecture (TTA), which is able to perform partial-dynamic reconfiguration to rectify problems that cannot be solved at the cellular level. Each TTA is, in turn, part of a larger multi-processor system which employs coarser grain reconfiguration to tolerate faults that cause a processor to fail. In this paper, we describe the details of operation of each layer of the SABRE hierarchy, and how these layers interact to provide a high systemic level of fault tolerance. © 2013 IOP Publishing Ltd

Secondary (additional) findings from the 100,000 Genomes Project: disease manifestation, healthcare outcomes and costs of disclosure

Purpose The UK 100,000 Genomes Project offered participants screening for additional findings (AFs) in genes associated with familial hypercholesterolaemia (FH) or hereditary cancer syndromes including breast/ovarian cancer (HBOC), Lynch, familial adenomatous polyposis, MYH-associated polyposis, multiple endocrine neoplasia, von Hippel-Lindau. Here we report disclosure processes, manifestation of AF-related disease, outcomes and costs. Methods An observational study in an area representing one-fifth of England. Results Data were collected from 89 adult AF recipients. At disclosure, among 57 recipients of a cancer predisposition-associated AF and 32 recipients of an FH-associated AF, 35% and 88% respectively had personal and/or family history evidence of AF-related disease. During post-disclosure investigations, four cancer-AF recipients had evidence of disease, including one medullary thyroid cancer. Six women with an HBOC AF, three women with a Lynch syndrome AF, and two individuals with a MEN AF elected for risk-reducing surgery. New hyperlipidaemia diagnoses were made in six FH-AF recipients, and treatment (re-)initiated for seven with prior hyperlipidaemia. Generating and disclosing AFs in this region cost £1.4m; £8,680 per clinically significant AF. Conclusion Generation and disclosure of AFs identifies individuals with, and without personal or familial evidence of disease, and prompts appropriate clinical interventions. Results can inform policy towards secondary findings

Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects*

In this paper we present a novel circuit for the on-line detection of transient and crosstalk faults affecting the interconnects of systems implemented using Field Programmable Gate-Arrays (FPGAs). The proposed detector features self-checking ability with respect to faults possibly affecting itself, thus being suitable for systems with high reliability requirements, like those for space applications. Compared to alternate solutions, the proposed circuit requires a significantly lower area overhead, while implying a comparable, or lower, impact on system performance. We have verified our circuit operation and self-checking ability by means of post-layout simulations

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects

In this paper we present a novel circuit for the on-line detection of transient and crosstalk faults affecting the interconnects of systems implemented using Field Programmable Gate-Arrays (FPGAs). The proposed detector features self-checking ability with respect to faults possibly affecting itself, thus being suitable for systems with high reliability requirements, like those for space applications. Compared to alternate solutions, the proposed circuit requires a significantly lower area overhead, while implying a comparable, or lower, impact on system performance. We have verified our circuit operation and self-checking ability by means of post-layout simulations

A novel dual-walled CNT bus architecture with reduced cross-coupling features

Carbon Nano Tubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, a novel bus architecture with low crosstalk features is proposed. It is made of dual-walled nanotubes (DWNTs) arranged in parallel. It achieves reductions up to 72% of the crosstalk-induced delay, and up to 76% for the crosstalk-induced peak voltage, at a modest area increase. Therefore, the proposed bus arrangement significantly improves performance and provides reliable operation in an interconnect. © 2006 IEEE

The other side of the timing equation: A result of clock faults

We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven in [15]). Therefore, new testing/DFT approaches are needed to avoid the dramatic impact of clock faults on product quality and operation in the field. Various possible approaches are discussed. © 2005 IEEE

Path (min) delay faults and their impact on self-checking circuits' operation

Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths ' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or wear out in the field would potentially also cripple the clock distribution network. Consequently, we should start considering also path (min) delay faults when designing on-line testable circuits, similar to what we currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults. © 2006 IEEE

On transistor level gate sizing for increased robustness to transient faults

In this paper we present a detailed analysis on how the critical charge (Q crit) of a circuit node, usually employed to evaluate the probability of transient fault (TF) occurrence as a consequence of a particle hit, depends on transistors' sizing. We derive an analytical model allowing us to calculate a node's Q crit given the size of the node's driving gate and fan-out gate(s), thus avoiding time costly electrical level simulations. We verified that such a model features an accuracy of the 97% with respect to electrical level simulations performed by HSPICE. Our proposed model shows that Q crit depends much more on the strength (conductance) of the gate driving the node, than on the node total capacitance. We also evaluated the impact of increasing the conductance of the driving gate on TFs' propagation, hence on Soft Error Susceptibility (SES). We found that such a conductance increase not only improves the TF robustness of the hardened node, but also that of the whole circuit. © 2005 IEEE

Accurate linear model for SET critical charge estimation

In this paper, we present an accurate linear model for estimating the minimum amount of collected charge due to an energetic particle striking a combinational circuit node that may give rise to a SET with an amplitude larger than the noise margin of the subsequent gates. This charge value will be referred to as SET critical charge (Q-SET}). Our proposed model allows to calculate the Q-SET} of a node as a function of the size of the transistors of the gate driving the node and the fan-out gate(s), with no need for time costly electrical level simulations. This makes our approach suitable to be integrated into a design automation tool for circuit radiation hardening. The proposed model features 96% average accuracy compared to electrical level simulations performed by HSPICE. Additionally, it highlights that Q-SET} has a much stronger dependence on the strength of the gate driving the node, than on the node total capacitance. This property could be considered by robust design techniques in order to improve their effectiveness. © 2006 IEEE